This invention relates generally to semiconductor chips, and in particular to flip chip die layout. More specifically, the invention relates to a die metal layout useful for flip chip packaging.
In semiconductor device assembly, a semiconductor chip (also referred to as an integrated circuit (IC) chip or "die") may be bonded directly to a packaging substrate, without the need for a separate leadframe or for separate I/O connectors (e.g. wire or tape). Such chips are formed with ball-shaped beads or bumps of solder affixed to their I/O bonding pads. During packaging, the chip is "flipped" onto its active circuit surface so that the solder balls form electrical connections directly between the chip and conductive traces on a packaging substrate. Semiconductor chips of this type are commonly called "flip chips".
Briefly, FIGS. 1A and B illustrate the concept of flip chip packaging. As shown in FIG. 1A, following semiconductor processing, the completed die 100 has an active circuit surface 102 on which are arranged metal pads (not shown) connected to the circuitry of the die by electrical traces (not shown). Solder balls 104 are bonded to these metal pads in order to provide an electrical connection for a packaging substrate 106. The flip chip die 100 is assembled into a package by "flipping" it onto a packaging substrate and connecting the solder balls 104 on the die 100 to the substrate 106.
As shown in FIG. 1B, the die 100 is aligned with and placed onto a placement site on the packaging substrate 106 such that the die's solder balls 104 are aligned with electrical traces (not shown) on the substrate 106. The die 100 and/or the packaging substrate 106 are then heated, to a temperature of about 220.degree. C. for example, causing the solder balls 104 to reflow and form electrical connections between the die 100 and the packaging substrate 106.
Subsequently, in conventional packaging procedures, this electrical connection is reinforced by mechanical connection of the die 100 to the substrate 106, typically using a thermally-cured epoxy underfill material (not shown). Further elements may also be added to the package to improve performance and reliability, for instance stiffeners and heat spreaders or heat sinks.
It should be noted that the foregoing figures are intended to be illustrative of the flip chip concept only and do not show all of the features of the die or packaging substrate, or the features in proportion with each other. For example, the solder balls 104 in proportion to the semiconductor die 100. In current designs, the die may have dimensions on the order of 0.5.times.0.5 inch (1 inch=2.54 cm) whereas the unbonded solder balls may have a diameter on the order of 4 to 5 mils (1 mil=10.sup.-3 inch=0.0254 mm).
In a preferred embodiment, the present invention is directed to the metal layout on a semiconductor die which is used to define the connections between the die and a packaging substrate. FIG. 2A shows a cross-sectional view of a conventional surface structure of a semiconductor flip chip, for instance, in a 0.35 .mu.m device size regime, prior to connection to a packaging substrate. The active surface 201 of the die 200 includes several metal pads 202, which are provided for supporting electrical connections between the die 200 and a packaging substrate (not shown), and a pattern of electrically conductive metal traces 204 which provide contacts between the pads 202 and input/output (I/O) slots on the die periphery (not shown). The die surface pads 202 and traces 204 are typically made of a patterned layer of aluminum or an aluminum alloy, such as aluminum copper (AlCu). The surface metal pads 202 are typically substantially octagonal in shape and about 105 to 130 .mu.m wide. The metal traces 204 running from the metal pads 202 to the I/O slots at the periphery of the die 200, and are typically about 10 to 20 .mu.m wide.
Following patterning of the surface metal pads 202 and traces 204 a passivation layer 206 composed of a dielectric material is deposited. Typically, the passivation layer 206 is composed of an oxide or nitride, such as silicon nitride, which is substantially conformally deposited, typically by chemical vapor deposition. A second level of metal pad, referred to as the "under bump metal pad" 208 ("UBM") is then deposited over the surface metal pads 202, connecting to them through a via 210 which is etched, for example, in the passivation layer 206 over a surface metal pad 202. The UBM 208 is typically composed of a plurality of layers. For example, a conventional UBM may be composed of a layer of copper (Cu), followed by a layer of nickel (Ni), and topped-off by a layer of gold (Au). A typical UBM is circular or hexagonal in shape and has a maximum span of about 5 to 20 .mu.m less than the surface metal bump to which it is attached; about 100 to 110 .mu.m. Solder bumps 212 are then attached to the UBMs 208 according to techniques well known in the art.
As semiconductor processing technology develops, semiconductor device size decreases, for example, from 0.35 .mu.m to 0.25 .mu.m transistor gate width and smaller, allowing the same number of devices to be placed on smaller dies. As noted above, metal traces 204 run from surface metal pads 202 to I/O slots (not shown) at the periphery of the die 200. Current designs for semiconductor dies have rows of six (6) surface metal pads 202. Four of the pads 202 are connected to one I/O slot each. The other two are connected to Vss and Vdd, respectively. As die sizes decrease, the width of I/O slots must correspondingly decrease. The width of an I/O slot defines the die's pitch, that is the spacing between rows of surface metal pads 202 on the die's active surface 201. In conventional 0.35 .mu.m device size flip chips, I/O slots are typically about 63 .mu.m wide; therefore the pitch of the metal pad rows on these chips is about 252 .mu.m (4.times.63 .mu.m). Therefore, the maximum allowable width of the surface metal pads 202 and the metal traces 204 on the chip, including appropriate spacing of about 2 to 5 .mu.m to prevent shorting, is about 252 .mu.m.
Improvements in process technology have recently made 0.25 .mu.m semiconductor devices viable. The corresponding decrease in the die size has resulted in the development of narrower I/O slots. As an example, I/O slots about 50 .mu.m wide have been developed for 0.25 .mu.m device size dies. As a result, die pitch for such chips has been reduced to about 200 .mu.m (4.times.50 .mu.m).
In order to accommodate such decreased pitch, current surface metal pad 202 and/or metal trace widths must be reduced, since any substantial further reduction in the space between pads and traces risks shorts and failure of the die 200. Reduction in the width of the metal traces 204 is undesirable since it results in increased electrical resistance. Therefore, it is preferable to reduce the width of the surface metal pads 202.
However, it has been discovered that reduction in the width of the surface metal pads produces stresses which may affect the reliability of the flip chip package. As shown in FIG. 2B, the surface metal pads 202' are reduced in size so that they are smaller (cover less die surface area) than the UBMs 208', while the width of the metal traces 204' is substantially unchanged. The narrowing of the metal pads 202' allows the combined width of the pads 202' and traces 204' to meet the reduced pitch requirement. But in the conventional configuration, with the traces outside of the die surface area covered by the UBM 208', the conformally deposited passivation material 206' will have indentations 220' between the surface metal pads 202' and the metal traces 204'. This is also true of the conventional structure depicted in FIG. 2A, however, whereas in the conventional structure the indentation 220 adjacent to a pad 202 is beyond the UBM 208 and does not affect its deposition, in the reduced pad size structure shown in FIG. 2B, the indentation 220' is underneath an outer portion 222' of the UBM 208'.
The UBM must be about the same size as in the conventional structure in order to reliably attach to and support a solder bump 212' of sufficient size to provide adequate space (about 70 to 90 .mu.m) between the electrically bonded die 200 and substrate for subsequent effective dispensation of a mechanically bonding underfill material. When an indentation 220' is within the UBM deposition region, it provides in a non-planar deposition substrate. This results in curling of the outer portions 222' of the CVD deposited UBM 208' which is deposited in substantial conformity with the dielectric substrate 206'. Non-uniform stress may occur in a solder bump 212' without a substantially flat surface for attachment. Such non-uniform stress negatively affects the long term reliability of the solder bump connection.
Thus, it would be desirable to have a flip chip metal layout which is compatible with reduced die pitches resulting from reduced device size environments without a substantial increase in electrical resistance or reliability concerns due to uneven solder bump stress.